Ferroelectric materials are materials in which, if an external voltage is applied to electric dipoles arranged in the material, a spontaneous polarization of the electric dipoles is generated. Application of a reverse external field to a ferroelectric material causes polarization of the electric dipoles in the opposite direction. Ferroelectric materials exhibit a hysteresis that is dependent on the magnitude and direction of the electric field. A memory device in which information is read or written from the device using the hysteresis of a ferroelectric material is referred to as a ferroelectric memory device. Typically, ferroelectric memory devices are non-volatile memory devices in which data can be retained even when power to the device is turned off.
A typical state of the art ferroelectric memory device is a non-volatile memory device that can be programmed using voltages of less than 5V. These devices typically are durable and do not consume much power—for example, they may draw less than 1 microampere of standby current. In light of these characteristics, ferroelectric memory devices have been regarded by many in the art as representing the next-generation of non-volatile memory devices. However, to achieve this status it is desirable to provide ferroelectric memory devices that are highly integrated.
A number of different cell structures for ferroelectric memory devices have been suggested to provide various of the characteristics that are desirable for next-generation non-volatile memory devices. For example, highly reliable ferroelectric memory devices have been proposed which have unit cells that comprise one transistor and one capacitor, a multi-layered line process, hot temperature retention, and read and write endurance.
In another approach, ferroelectric memory devices have been proposed that, similar to a DRAM memory device, include a transistor and a ferroelectric capacitor that are electrically interconnected. Such an approach is disclosed in U.S. Pat. No. 5,119,154 entitled “FERROELECTRIC CAPACITOR AND METHOD FOR FORMING LOCAL INTERCONNECTION” which is assigned to Micron Technology, Inc.
As noted above, achieving high-integration in a ferroelectric memory device is another important consideration. The degree of device integration sets a limit on the maximum size of the unit cells of the device. Two important processes for achieving such high integration are materialization of the one transistor-one capacitor structure and shrink-down technology for reducing the size of the ferroelectric capacitor.
FIG. 1 illustrates a conventional method of connecting source/drain regions of the transistor in the unit cell of a ferroelectric memory device to the ferroelectric capacitor using a plug. The method of connecting the source/drain regions of the transistor to the ferroelectric capacitor using a plug that is illustrated in FIG. 1 is disclosed in U.S. Pat. No. 5,854,104 entitled “PROCESS FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A FERROELECTRIC CAPACITOR” that is assigned to Sharp Inc.
The conventional ferroelectric memory device of FIG. 1 may be formed through the following steps. First, a transistor that includes a gate electrode 4 is formed in the semiconductor substrate 1. Next, an interlayer dielectric 7 is formed. Then a bottom electrode of a capacitor is formed as a TiN layer 12 and a Pt layer 13. Next, a capacitor ferroelectric 14 is formed, and the top electrode of the capacitor is formed by sequentially stacking a Pt layer 15, a TIN layer 16 and an alumina layer 17.
As shown in FIG. 1, the layers 12, 13 comprising the bottom electrode of the capacitor are electrically connected to a plug 11 that penetrates the interlayer dielectric 7. The semiconductor substrate 1 includes an isolation layer 2 and the gate electrode 4 of the transistor is in contact with a bit line 6. The drain region 5b in the semiconductor substrate is in contact with the plug 11. The device also includes a gate insulation layer 3, a diffusion prevention layer 8, a barrier 10 and an insulation layer 18.
The ferroelectric material of the dielectric of the capacitor is formed by depositing the ferroelectric material between the bottom electrode of the capacitor and the interlayer dielectric. The ferroelectric capacitor conventionally is formed using an etching process. In forming the capacitor ferroelectric, the ferroelectric material is typically deposited in non-crystalline state. A heat treatment is then applied that crystallizes the ferroelectric material.